From code
to pins.

00 / The brief, decoded

A programmable instrument
for talking to hardware.

Original: Benjamin Devlin & Anish Singhani, Jane Street, September 10, 2026 ↗. This is an independent learning companion, not a Jane Street publication. Rules checked November 1, 2026; the original remains authoritative.

Our starting decision: a guided overview first, followed immediately by a register-and-counter exercise. A broad electronics course would postpone the useful feedback. You need enough circuit intuition to challenge AI’s output, then measurements to guide architecture. Transistor physics can deepen alongside the work.

01 / The mental shift

You describe a machine.
Then the machine runs.

In software, x = a + b usually asks an existing processor to perform an operation. In a hardware description, an expression can describe an adder that physically exists and continuously responds to its inputs. Two independent adders can operate at the same time. More parallel work often means more circuit area.

always @(posedge clk) begin
  a <= b;
  b <= a;
end

RTL means register-transfer level: describe stored state and the logic between registers. Verilog/SystemVerilog are hardware description languages; Hardcaml generates RTL from OCaml. A source loop may replicate hardware during elaboration; it does not automatically imply a CPU executing repeated instructions. Some constructs are for simulation only. Practice clocked versus combinational blocks →

02 / One byte on a wire

“Send A” is a timed
sequence of voltages.

UART sends serial bits without a shared clock wire. Both ends agree on the bit rate and frame format. In common 8N1, the idle line is high, a low start bit begins the frame, eight data bits follow least-significant bit first, and a high stop bit ends it. N means no parity bit. UART introduction, Analog Devices →

At a hypothetical 24 MHz engine clock, one cycle takes 41.67 ns. Dividing by 208 produces about 115,384.6 bits/s, +0.16% from 115,200. That is a divider calculation, not a promise of timing closure or a receiver tolerance budget. Start-bit detection latency and the other endpoint’s clock error also matter.

Three protocols, three kinds of difficulty

SPI: Analog Devices · I²C: NXP specification, §3

03 / A candidate architecture

A small instruction set.
A very explicit contract.

This is a teaching sketch, not an implemented or measured competition entry. It separates the host’s irregular timing from the pin engine’s controlled timing.

Give every instruction a precise transition rule: which registers change, when a pin changes, how many clock edges elapse, and what stalls it. Define what happens if a FIFO is empty or full. Blocking in the middle of a frame can break the protocol even if every transmitted bit is logically correct.

// Illustrative ISA notation, not executable RTL.
DRIVE TX, 0, HOLD=208   // start bit: exactly 208 cycles total
SHIFT_OUT TX, HOLD=208 // emit next low bit, shift, hold
...                    // eight data bits in all
DRIVE TX, 1, HOLD=208   // stop bit

Our hypothetical HOLD includes the instruction’s emission cycle. Other semantics are possible; specifying the choice prevents off-by-one errors. A synchronous instruction memory may add fetch latency. You must account for that in the architecture instead of assuming each instruction takes one cycle.

Study RP2040 PIO for one concrete approach: short programs, shift registers, small queues and deterministic I/O. TI PRU is another reference with a different balance of general computation and direct I/O. Learn the tradeoffs before choosing how yours differs. Raspberry Pi PIO overview →

04 / Getting to silicon

The compiler has a
physical backend.

ASIC means application-specific integrated circuit: its manufactured logic and interconnect are fixed. Firmware can remain changeable if you design writable program memory and a loader. An FPGA contains configurable logic and routing, so it is useful for prototyping, but passing on an FPGA does not establish that the ASIC will meet its own timing or electrical requirements.

1. Specification → RTLWrite the behavior, interfaces, reset and cycle semantics. Simulate the hardware description.
2. Synthesis → netlistMap the description to gates and storage cells from a technology library. Inspect area and inferred memories.
3. Place, clock, routePosition cells, distribute the clock and connect wires. Wire lengths now affect delay.
4. Checks → GDS → fabricationCheck timing, layout design rules and connectivity. GDS describes layout geometry for manufacturing; tapeout is the handoff.

Yosys synthesis overview · Tiny Tapeout: RTL to layout, with video · Competition-linked CMOS5L template

Use AI aggressively. Make evidence independent.

AI can draft RTL, explain waveforms, write an assembler and propose tests. The valuable skill is deciding what must be true and checking it through a different route. An implementation and a test copied from the same mistaken assumption can agree perfectly.

• Behavior: send programs and bytes through the real simulator/CLI; independently decode pin traces. Include reset mid-frame, empty/full queues, unexpected input and back-to-back transactions.
• Formal properties: prove a specific claim under explicit assumptions—for example, no active-high drive in open-drain mode. A bounded proof is limited to its horizon unless a complete proof is established.
• Physical feasibility: keep synthesis and routed timing reports for the exact source and constraints. Passing simulation does not prove timing closure.
• Hardware acceptance: when available, use an FPGA and a real peer device with captured traces; later validate fabricated silicon. Label simulation, FPGA results and silicon results separately.

For a strong engineering portfolio, keep short design decisions, reproducible commands, failing examples, measured tradeoffs and a demo that another person can run. That gives reviewers evidence of your judgment as well as AI’s output.

05 / Start here today

One session.
One explainable result.

Spend about 60–90 minutes. The target is to explain every register and clock edge in a tiny design. No hardware purchase is needed for this first session.

1. Read and predict · 15 minutes

   Use the three experiments above. Explain why the registers swap, why UART 8N1 needs ten bit periods per byte, and why an I²C device releases a line.

2. Practice HDL · 30 minutes

   On HDLBits, do a wire, a mux, a D flip-flop, a resettable flip-flop and a counter. Skip repetitive elementary Boolean exercises once comfortable. Predict behavior before using the checker.

3. Write the first contract · 15 minutes

   Specify a transmitter: clock rate, baud divider, 8N1 format, idle level, reset behavior and what a send request means while busy. For a 24 MHz / 208-cycle example, one ten-bit frame occupies 2,080 engine cycles. Choose whether requests queue or are rejected; don’t leave it implicit.

4. Next build · one UART transmitter

   Implement and simulate that contract, then decode its waveform independently. Only after this works should the fixed state machine become programmable. Synthesize early enough to let area and timing influence the instruction set.

The smallest useful reading list

Use these in order. Time boxes are suggested study time, not video runtimes.

Defer full CPU courses, transistor fabrication detail, USB/Ethernet and clever multi-engine designs. Return to them when a measured design need appears. Hardcaml is worth evaluating after you can read basic RTL; there is no need to choose the final implementation language today.